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Question Maple Story — CAP DMA 75T Firmware & NGS/BlackCipher Setup

byte_corvus

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Staring at a bricked board after a Vivado flash is a rite of passage for anyone moving into the DMA scene. If you just grabbed a CAP DMA 75T and tried to roll your own firmware for Maple Story, you've likely hit the first wall: config space validation.

The NGS (BlackCipher) Situation
Nexon Game Security (NGS) isn't the most sophisticated anti-cheat on the market compared to Vanguard, but it’s definitely not sleeping on generic PCILEECH signatures. If you run the stock PCILEECH firmware without modifying the VID/PID and the device description strings, you are basically begging for a manual flag or an instant kick once the heartbeat checks clear.

Common Firmware Pitfalls
When you say the "board is not working" after modifying the VID/HID in Vivado, it usually points to one of three things:
  1. The bitstream failed to generate correctly because of a constraint mismatch.
  2. The TLP (Transaction Layer Packet) settings or the configuration space was corrupted during the edit.
  3. The flashing process via JTAG didn't verify correctly.

Is VID/HID Modification Mandatory?
Short answer: Yes. Long answer: If you want any semblance of longevity for your account, you cannot use the default IDs. NGS scans for hardware IDs associated with development boards and known DMA hardware. However, it's not just about changing "4 lines." You need to ensure the entire configuration space looks like a legitimate peripheral (like a network card or a storage controller) to avoid detection by software-based timing checks or simple ID blacklisting.

1. Always verify your board is still alive by flashing the original, unmodified PCILEECH BIN file.
2. When editing in Vivado, Ensure your pin constraints match the 75T target. A 35T bitstream will not work on a 75T.
3. Check your device manager — if the board shows up as a "PCI Serial Port" or an unknown device with an error code 10, your VID/PID modification broke the driver handshake.

If you're stuck on the BIN generation, you might want to look into how the PCIe IP core handles those attributes. Simply changing strings in a header file isn't always enough if the block design isn't updated to reflect the new ID values during the synthesis stage.

Are you getting any specific errors in Vivado during the implementation stage, or is the board just not appearing in the PCIe tree at all?
 
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